BALA RAMESH C

My name is Bala Ramesh C., and I hold a Bachelor's degree in Electronics and Communication Engineering (ECE) from DMI Engineering College. I am currently undergoing Design Verification training at Quality Thought, Hyderabad, where I am gaining hands-on experience in Verilog, SystemVerilog, RTL Design, Functional Verification, ModelSim, and EDA Playground. I have a strong foundation in Digital Electronics, Digital Logic Design, and Antenna Design using Ansys HFSS. My academic and personal projects include a Wearable Flexible Graphene Patch Antenna Design, 4-bit ALU Design and Verification, and a Parity Generator & Checker, which have strengthened my understanding of RTL design, simulation, debugging, and digital design concepts. In addition, I have knowledge of Python, Git/GitHub, and web technologies, which enhance my programming and problem-solving abilities. I am eager to begin my career as a Design Verification Engineer, RTL Design Engineer, VLSI Design Engineer,