Sireesha jonnada

Recent Electronics and Communication Engineering graduate with hands-on expertise in RTL Design, Functional Verification, and Digital Systems Architecture. Highly proficient in Verilog, SystemVerilog, and VHDL with strong practical knowledge of Digital Electronics, CMOS fundamentals, Computer Architecture, and Microprocessors. Experienced in simulation, logic synthesis, timing analysis (STA), and debugging using industry-standard EDA tools like Xilinx Vivado and Cadence Virtuoso targeting ASIC/FPGA design flow.